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[VHDL-FPGA-Verilog] DDS

Description: FPGA产生DDS，未使用IP核，内含VERILOG程序-FPGA generates DDS, unused IP core, containing VERILOG program
Platform: | Size: 585728 | Author: bodao | Hits:

[Embeded-SCM Develop] DDS_Ad9854_Verilog

Description: DDS控制模块 AD9854 VERILOG-DDS control module AD9854 VERILOG
Platform: | Size: 820224 | Author: 盛夏 | Hits:

[Other] dds_compiler_v4_0

Description: Verilog的DDS实现正弦波输出。这个模块是不可综合的，但是已经综合了，-Verilog DDS
Platform: | Size: 16384 | Author: mingtian | Hits:

[VHDL-FPGA-Verilog] DDS_TLC5620

Description: DDS函数信号发生器 tlc5620 verilog-dds tlc5620 verilog
Platform: | Size: 3838976 | Author: 董辉辉 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 采用硬件描述语言verilog进行DDS变换的实现的代码-Using hardware description languages Verilog implementation of DDS converter code
Platform: | Size: 1024 | Author: 何晨光 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 用Verilog HDL 编写的一个最基本的DDS程序，发生正弦波-Verilog HDL prepared with a basic DDS program, the occurrence of a sine wave
Platform: | Size: 890880 | Author: 董航 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: Verilog HDL实现FPGA的DDS功能，含有实验原理与代码程序-FPGA Verilog HDL realize the DDS function, principles and codes containing experimental procedures
Platform: | Size: 893952 | Author: 秦天沐 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于fpga的正余弦波形发生器，Verilog代码，测试通过。-Cosine waveform generator fpga based, Verilog code, the test passes.
Platform: | Size: 4471808 | Author: 黄迟 | Hits:

[VHDL-FPGA-Verilog] DDS-MY-WORK-1

Description: FPGA模拟数字信号发生器DDS verilog-FPGA analog and digital signal generator DDS verilog
Platform: | Size: 10680320 | Author: luowang | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于fpga的DDS详细设计方案 verilog语言 正弦计算器则对该相位值计算数字化正弦波幅度（芯片一般通过查表得到）。DDS芯片输出的一般是数字化的正弦波，因此还需经过高速D/A转换器和低通滤波器才能得到一个可用的模拟频率信号。-Direct Digital Synthesizer base on fpga use verilog Sine calculator to calculate the value of the digital phase sine wave amplitude (chips generally obtained through look-up table). Generally digitized sine wave output of DDS chip, and therefore need to go through the high-speed D/A converter and a low pass filter to get an analog frequency signal available.
Platform: | Size: 5949440 | Author: 网窝囊 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: verilog编写，使用fpga中dds手法，可以输出任意波形的发生信号。-verilog write, use the dds fpga way, you can output an arbitrary waveform signal occurs.
Platform: | Size: 506880 | Author: 李俊 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 在quartus软件上，采用verilog实现DDS功能。- using verilog realize DDS function On quartus software.
Platform: | Size: 2166784 | Author: 刘云 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 这是本人在学校做的一个DDS信号发生器，频率相位可调。输入时钟50Mhz-DDS phase frequency adjustable Verilog
Platform: | Size: 2437120 | Author: wen show | Hits:

[VHDL-FPGA-Verilog] DDS

Description: Verilog实现DDS线性调频，Verilog实现DDS线性调频-Verilog implementation of DDS linear FM，Verilog implementation of DDS linear FM
Platform: | Size: 1024 | Author: youyou | Hits:

[VHDL-FPGA-Verilog] DDS

Description: FPGA基于FPGA的DDS设计verilog程序-FPGA DDS project verilog procedure
Platform: | Size: 10240 | Author: 吴汉 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: FPGA实现三通道DDS信号源Verliog程序-FPGA to achieve three-channel DDS signal source Verilog program
Platform: | Size: 9389056 | Author: 果粒橙 | Hits:

[VHDL-FPGA-Verilog] DDS(ok)

Description: 制作ROM正弦表并填充FPGA内部ROM，通过调用内部数据实现正弦波输出，开发环境quartusii , 语言verilog , 调试通过 ， 附有modelsim调试结果。-Make ROM sine table and fill the ROM internal FPGA, by calling the internal data to achieve the sine wave output, development environment QuartusII, Language Verilog, debugging through, with Modelsim debugging results.
Platform: | Size: 10149888 | Author: PrudentMe | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于FPGA，Verilog语言编写的DDS信号发生器，可生成方波、正玄波，三角波。-Based FPGA, Verilog language DDS signal generator that generates a square wave, sine wave, triangle wave.
Platform: | Size: 131072 | Author: 梁世强 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 这是一个用Verilog语言实现的一个数字信号产生器算法-This is a use Verilog language implementation of a digital signal generator is presented
Platform: | Size: 2735104 | Author: liu liushuai | Hits:

[VHDL-FPGA-Verilog] DDS-verilog

Description: DDS是直接数字式频率合成器（Direct Digital Synthesizer）的英文缩写，是一项关键的数字化技术。与传统的频率合成器相比，DDS具有低成本、低功耗、高分辨率和快速转换时间等优点，广泛使用在电信与电子仪器领域，是实现设备全数字化的一个关键技术。文件写了一个DDS的例程，并编写了TB文件。-DDS is a direct digital synthesizer (Direct Digital Synthesizer) of the English abbreviation, is a key digital technology. Compared with the traditional frequency synthesizer, DDS has the advantages of low cost, low power consumption, high resolution and fast conversion time. It is widely used in the field of telecommunication and electronic instrument, which is a key technology to realize the whole digitization of equipment. The file was written with a DDS routine and a TB file was written.
Platform: | Size: 2048 | Author: 林威 | Hits:
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